Download e-book for kindle: Analog Circuit Design: Low Voltage Low Power; Short Range by Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto

By Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto

ISBN-10: 9400719256

ISBN-13: 9789400719255

Analog Circuit layout comprises the contribution of 18 tutorials of the 20 th workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and useful layout principles within the zone of analog circuit layout. each one half is gifted by means of six specialists in that box and cutting-edge info is shared and overviewed. This e-book is quantity 20 during this profitable sequence of Analog Circuit layout, delivering beneficial info and perfect overviews of:

Topic 1 : Low Voltage Low strength, chairman: Andrea Baschirotto
Topic 2 : brief diversity instant Front-Ends, chairman: Arthur van Roermund
Topic three : energy administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational insurance additionally makes it appropriate to be used in a sophisticated layout path.

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Extra resources for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

Example text

2 Step-Wise Charging Another method to reduce the energy needed to charge a capacitor from 0 to V is to perform that operation not in one but in several sequential steps [4]. Switching in a 42 J. Craninckx b a VN N V2 2 V N RN, CN 2 R2, C2 CT CT V1 R1, C1 1 1 CL 0 R0, C0 0 CL Fig. 3 (a) Step-wise charging of a capacitive load; (b) using large ‘tank’ capacitors for the intermediate voltages [4] 2 single step takes an energy of E1 step D CV 2 . 1) This configuration is shown in Fig. 3, where it is also shown that there is no need for a separate circuit to generate the intermediate voltages.

M. 9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 382–383 24. C. P. 5 mW SAR assisted 2-stage pipeline ADC, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2010, pp. 239–240 25. A. Verma, B. Razavi, A 10-bit 500-MS/s 55-mW CMOS ADC. IEEE J. Solid-State Circuits 44(11), 3039–3050 (2009) 26. W. , A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J. Solid-State Circuits 36(12), 1931–1936 (2001) 27.

S. Kawahito, Low-power design of pipeline A/D converters, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2006, pp. 505–512 21. -C. Huang, T,-C. 5 mW pipelined ADC with a time sharing technique, in ISSCC Digest of Technical Papers, San Francisco, CA, USA, Feb 2010, pp. 300–301 22. P. 13um CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Dec 2006, pp. 832–841 23. M. 9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 2010, pp.

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Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC by Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto


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